A PLL (Phase Locked Loop) produces an output clock which is in phase with the input clock and whose frequency is greater than or equal to the input frequency. The lock circuit in the PLL detects when the output clock is in phase with the input clock and sets its lock bit accordingly (`1` when locked). The existing lock circuit used for the purpose as illustrated in FIG. 1 provides a specific way to set the lock bit, so the designer knows the exact condition which must be satisfied before the lock bit turns on. The problem with the existing circuit is the process of unsetting the lock bit which is very unpredictable. As a result, when the circuit unlocks, the designer cannot identify a specific condition which must have existed for it to do so, and this persisting problem is addressed by our invention.